Axi4 passive vip#391
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martin-velay
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I have added some comments, but I am still not done, I'll do another batch later. There are still some coding style issues
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| // This AXI4 VIP shall be always UVM_PASSIVE on top level | |||
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The copyright header is missing
| typedef enum bit[2:0] { | ||
| mst0 = 0, | ||
| slv0 = 1, | ||
| slv1 = 2, | ||
| slv2 = 3, | ||
| slv3 = 4 | ||
| } axi_if_t; |
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Would it be possible to change the field names into something more explicit like that maybe:
| typedef enum bit[2:0] { | |
| mst0 = 0, | |
| slv0 = 1, | |
| slv1 = 2, | |
| slv2 = 3, | |
| slv3 = 4 | |
| } axi_if_t; | |
| typedef enum bit[2:0] { | |
| mst0_cva6 = 0, | |
| slv0_sram = 1, | |
| slv1_mailbox = 2, | |
| slv2_tl_xbar = 3, | |
| slv3_dram = 4 | |
| } axi_if_t; |
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top_pkg field names are used.
| // AXI VIP configuration | ||
| axi_cfg = new[NUM_OF_AXI_IFS]; | ||
| env.cfg.m_axi_cfg = new[NUM_OF_AXI_IFS]; | ||
| foreach(axi_cfg[i]) begin |
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Nit: you need a space here and same below for the case. Can you please check else where in your code that you follow this rule.
https://github.com/lowRISC/style-guides/blob/master/VerilogCodingStyle.md#space-around-keywords
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| foreach (actual_q[s]) foreach (actual_q[s][i]) if (actual_q[s][i].size() > 0) | ||
| `uvm_error("SCB_DRAIN", $sformatf("Slave trans on %s (ID %h) never reached Master", s, i)) | ||
| endfunction : check_phase No newline at end of file |
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You need to configure your editor to make sure you insert an empty line at the end of each file (it's also part of the coding rules somewhere)
| string slave_name; | ||
| bit [63:0] start_addr; | ||
| bit [63:0] end_addr; | ||
| } local_addr_range_t; |
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Can you move this typedef into the env_pkg
| int unsigned master_id_width = 4; | ||
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| // Analysis Implementation Ports | ||
| `uvm_analysis_imp_decl(_mst0) |
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In the names if we can make it clearer which block is connected, as commented in the env_pkg, that would be better for debug purposes
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Updated using the top_pkg names
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| // Queues to handle out-of-order monitor arrivals | ||
| // [SlaveName][MaskedID] | ||
| axi4_vip_item expect_q[string][bit[63:0]][$]; // Master arrived first |
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Is this 64 bits width linked with top_pkg::AxiDataWidth? It's better to point to a pkg value, this should be applied wherever required in this PR
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This is ID width to handle when the interconnect extends the ID width to be able to back-route the transactions to the managers. However, good spot, the scoreboard cuts the unnecessary bits before anything is pushed to this queue. Replaced by parameter.
| mem_map.push_back('{"slv0", 64'h1000_0000, 64'h1001_FFFF}); | ||
| mem_map.push_back('{"slv1", 64'h2001_0000, 64'h2001_FFFF}); | ||
| mem_map.push_back('{"slv2", 64'h4000_0000, 64'h4FFF_FFFF}); | ||
| mem_map.push_back('{"slv3", 64'h8000_0000, 64'hBF7F_FFFF}); |
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Here, the same applies, could you point at the pkg values please axi_addr_start_t
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| function string top_chip_dv_axi_scoreboard::decode_addr(bit [63:0] addr); | ||
| foreach (mem_map[i]) begin | ||
| if (addr >= mem_map[i].start_addr && addr <= mem_map[i].end_addr) |
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You need to add the begin...end for each if whenever it doesn't fit on a single line as a rule. But as we talk about DV here, I'd prefer to add the begin...end and always jump a line this will facilitate breakpoint debug
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| function void top_chip_dv_axi_scoreboard::check_phase(uvm_phase phase); | ||
| super.check_phase(phase); | ||
| foreach (expect_q[s]) foreach (expect_q[s][i]) if (expect_q[s][i].size() > 0) |
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This should be break down into multi lines and I think one foreach is useless:
| foreach (expect_q[s]) foreach (expect_q[s][i]) if (expect_q[s][i].size() > 0) | |
| foreach (expect_q[s][i]) begin | |
| if (expect_q[s][i].size() > 0) begin | |
| `uvm_error("SCB_DRAIN", $sformatf("Master req for %s (ID %h) never reached Slave", s, i)) | |
| end |
| // maximum supported bus widths | ||
| `define AXI4_MAX_ID_WIDTH 16 | ||
| `define AXI4_MAX_ADDR_WIDTH 64 | ||
| `define AXI4_MAX_DATA_WIDTH 512 |
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Is there a reason why DATA_WIDTH 1024 is not supported?
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Updated to 1024.
| if (current_burst == null) current_burst = axi4_vip_item::type_id::create("w_burst"); | ||
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| current_burst.dir = AXI_WRITE; | ||
| current_burst.wdata.push_back(vif.monitor_cb.wdata & ((64'h1 << m_cfg.m_data_width) - 1)); |
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Shouldn't this be 512'h1 (or 1024'h1) for all rdata and wdata types?
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Updated with the given define.
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| // Local Address Map Struct | ||
| typedef struct { | ||
| string slave_name; |
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Nit: the new nomenclature of AXI uses manager and subordinate.
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Yes, we talked about this. Is it better if the naming matches the AXI standard or the current RTL. I know, the new standard uses manager and subordinate, but the RTL uses master and slave.
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Good point. I'd say that we should follow the latest nomenclature with manager/subordinate. So it might be that the RTL needs to be changed? But from our concern in this VIP, as its purpose goes beyond this particular DUT eventually, I'd suggest to use the new wording. Do you think there will be some confusing piece of code where the 2 kinds will live together?
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Updated names.
| begin | ||
| bit [63:0] addr = (tr.dir == AXI_WRITE) ? tr.awaddr : tr.araddr; | ||
| bit [63:0] id = (tr.dir == AXI_WRITE) ? tr.awid : tr.arid; | ||
| // Note: resp logic simplified here for example; normally bit-sliced per beat |
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Can you please formulate this comment more precise?
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This is a legacy comment from a previous version. Thanks for spotting it. Removed.
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| bit m_has_checker = 1; | ||
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| // actual bus widths (<= max defines) | ||
| int unsigned m_id_width = 16; |
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It does not really matter, because the configuration object is set in the test base. However, it does not hurt. Updating.
rswarbrick
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Here are some initial notes. I've got half way through axi4_vip_monitor.svh from the first commit.
| // Licensed under the Apache License, Version 2.0, see LICENSE for details. | ||
| // SPDX-License-Identifier: Apache-2.0 | ||
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| `ifndef AXI4_VIP_CFG_SVH |
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Why have we got include guards here? They make me raise my eyebrows: fusesoc is supposed to avoid us needing this...
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If you have a process to avoid double definition, I can remove the guards. However, they are pretty useful for larger projects.
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Firstly, most of the files in question are included by axi4_vip_pkg.sv. Even without any package manager, something has gone VERY wrong if you end up needing include guards on e.g. axi4_vip_cfg.svh.
But you also shouldn't need include guards on axi4_vip_pkg.sv. As you say, things can go wrong if you don't have a package manager (so you end up having to hack together something with include guards). The solution is to use one. This project uses fusesoc, which should solve the problem nicely.
As such, I strongly believe the correct path is to avoid littering the code with extra cruft.
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Okay, removing.
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One last include guard left! :-) I think the monitor needs to lose it too.
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@rswarbrick Thank you very much for the detailed review. I believe, all comments are addressed now. |
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| endtask : collect_aw_channel | ||
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| task axi4_vip_monitor::collect_w_channel(); | ||
| bit [`AXI4_MAX_DATA_WIDTH-1:0] data_mask = (1'b1 << m_cfg.m_data_width) - 1; |
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Thanks for defining the masks like I suggested. Annoyingly, this currently assumes that all the signals are at most 32 bits wide (because 1'b1 << abc gets expanded to the width of abc, so 1'b1 << 32 isn't going to do what you want).
I think this is going to be a problem for the data variables here, because m_cfg.m_data_width in the example is 1024. I think something like this would work, but it's really ugly:
bit [`AXI4_MAX_DATA_WIDTH-1:0] data_mask = (`AXI4_MAX_DATA_WIDTH'b1 << m_cfg.m_data_width) - 1;I'm convinced this was a very bad suggestion from me (sorry)! I guess the best thing is something like this:
bit [`AXI4_MAX_DATA_WIDTH-1:0] data_one = 1;
bit [`AXI4_MAX_DATA_WIDTH/8-1:0] strb_one = 1;
bit [`AXI4_MAX_USER_WIDTH-1:0] user_one = 1;
bit [`AXI4_MAX_DATA_WIDTH-1:0] data_mask = (data_one << m_cfg.m_data_width) - 1;
bit [`AXI4_MAX_DATA_WIDTH/8-1:0] strb_mask = (strb_one << (m_cfg.m_data_width/8)) - 1;
bit [`AXI4_MAX_USER_WIDTH-1:0] user_mask = (user_one << m_cfg.m_user_width) - 1;
axi4_vip_item current_burst;
forever begin
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The version that you've now got is good because it gets the widths right. Unfortunately, the lines end up enormous:
// Optimized strobe mask width (DATA_WIDTH / 8)
bit [`AXI4_MAX_DATA_WIDTH-1:0] data_mask = (`AXI4_MAX_DATA_WIDTH'(1) << m_cfg.m_data_width) - 1;
bit [(`AXI4_MAX_DATA_WIDTH/8)-1:0] strb_mask = ((`AXI4_MAX_DATA_WIDTH/8)'(1) << (m_cfg.m_data_width/8)) - 1;
bit [`AXI4_MAX_USER_WIDTH-1:0] user_mask = (`AXI4_MAX_USER_WIDTH'(1) << m_cfg.m_user_width) - 1;(the middle line is 110 characters).
I'd probably suggest the example I wrote above, where the long lines are 88.
| - lowrisc:dv:xbar_macros | ||
| - lowrisc:dv_dpi_c:uartdpi:0.1 | ||
| - lowrisc:dv_dpi_sv:uartdpi:0.1 | ||
| - lowrisc:dv:axi4_vip:0.1 |
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I think you may as well squash this commit into the following one. The dependency is a bit pointless to add until we use it and axi_vip_connections.sv doesn't even exist until the next commit.
What's more, the dependency is in the wrong place. I think you actually need it on top_chip_dv_env, don't you?
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The idea here was, you need to add the vip first and then you can integrate it.
Could you please send me a link which file are you referring to? I cannot find top_chip_dv_env.
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Since the VIP configuration is done in the test base, top_chip_dv_env.core is not enough.
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I'm sorry, but I'm not sure that's quite right (or maybe I don't understand your message).
To make things really explicit:
lowrisc:mocha_dv:top_chip_simdepends onlowrisc:mocha_dv:top_chip_dv_testlowrisc:mocha_dv:top_chip_dv_testdepends onlowrisc:mocha_dv:top_chip_dv_envlowrisc:mocha_dv:top_chip_dv_envdepends onlowrisc:dv:axi4_vip:0.1
Signed-off-by: Csaba Kiss <csaba.kiss@semify-eda.com>
Signed-off-by: Csaba Kiss <csaba.kiss@semify-eda.com>
…top UVM environment Signed-off-by: Csaba Kiss <csaba.kiss@semify-eda.com>
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Thanks for addressing lots of comments! To make sure nothing gets lost, the remaining items from me are: I'll start reviewing the scoreboard commit now. |
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| endclass : top_chip_dv_axi_scoreboard | ||
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| //------------------------------------------------------------------------------ |
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I think I've said this elsewhere, but there's really no need for this sort of comment. It's analogous to
// This is an addition.
a = b + c;Clearly a pointless comment! :-)
| super.build_phase(phase); | ||
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| // Address Mapping Configuration | ||
| mem_map.push_back('{"sub0_sram", (top_pkg::SRAMBase), (top_pkg::SRAMBase + top_pkg::SRAMLength - 1)}); |
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This is clever, but the lines are very long.
I'd suggest avoiding the repeating the names by using a function like this:
function void top_chip_dv_axi_scoreboard::add_mem_range(string name,
bit [63:0] start_addr,
bit [63:0] addr_size);
bit [63:0] end_addr = start_addr + addr_size - 1;
mem_map.push_back('{name, start_addr, end_addr});
endfunctionThen these lines end up looking like this one:
add_mem_range("sub0_sram", top_pkg::SRAMBase, top_pkg::SRAMLength);| mem_map.push_back('{"sub3_dram", (top_pkg::DRAMBase), (top_pkg::DRAMBase + top_pkg::DRAMLength - 1)}); | ||
| endfunction : build_phase | ||
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| // Robust masking using 64-bit context for the shift operation |
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Documentation comments belong by the declaration of the function, not its implementation.
| // External Method Declarations | ||
| extern function new(string name, uvm_component parent); | ||
| extern virtual function void build_phase(uvm_phase phase); | ||
| extern protected function bit [63:0] get_masked_id(bit [63:0] raw_id); |
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These functions need documentation comments that explain what they do.
| if (act.dir == AXI_WRITE) begin | ||
| if (act.awaddr !== exp.awaddr || act.awlen !== exp.awlen || | ||
| act.awsize !== exp.awsize || act.awburst !== exp.awburst) begin | ||
| `uvm_error("SCB_ATTR_WR", $sformatf("Write Attribute mismatch on %s ID:%h", slv, mid)) |
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I think this probably needs to print the mismatching values (and similarly for the other errors in this function).
| uvm_config_db#(virtual axi4_vip_if)::set(null, "*.m_sub_axi_Mailbox.*", "vif", axi4_sub_if[top_pkg::Mailbox]); | ||
| uvm_config_db#(virtual axi4_vip_if)::set(null, "*.m_sub_axi_TlCrossbar.*", "vif", axi4_sub_if[top_pkg::TlCrossbar]); | ||
| uvm_config_db#(virtual axi4_vip_if)::set(null, "*.m_sub_axi_DRAM.*", "vif", axi4_sub_if[top_pkg::DRAM]); | ||
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| top_pkg::axi_hosts_t axi_mgr_name; | ||
| top_pkg::axi_devices_t axi_sub_name; |
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These should be scoped inside the foreach blocks.
| axi_mgr_cfg = new[NUM_OF_MGR_AXI_IFS]; | ||
| env.cfg.m_axi_mgr_cfg = new[NUM_OF_MGR_AXI_IFS]; |
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Is that correct? It seems a bit weird to have two arrays with the same items. Can't we just have the first line and then (after the loop) have something like env.cfg.m_axi_mgr_cfg = axi_mgr_cfg; ?
| env.cfg.m_axi_mgr_cfg = new[NUM_OF_MGR_AXI_IFS]; | ||
| foreach (axi_mgr_cfg[i]) begin | ||
| axi_mgr_name = top_pkg::axi_hosts_t'(i); | ||
| axi_mgr_cfg[i] = axi4_vip_cfg::type_id::create(.name($sformatf("m_axi_%s_cfg", axi_mgr_name.name())), .parent(this)); |
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Overly long line. Also, the naming doesn't look quite right: axi_mgr_name.name() is a little weird :-)
Something like this, maybe?
axi_mgr_cfg = new[NUM_OF_MGR_AXI_IFS];
foreach (axi_mgr_cfg[i]) begin
axi_host_t host = top_pkg::axi_hosts_t'(i);
string cfg_name = $sformatf($sformatf("m_axi_%s_cfg", host.name())
axi_mgr_cfg[i] = axi4_vip_cfg::type_id::create(cfg_name, this);
case (host)
top_pkg::CVA6: begin
axi_mgr_cfg[i].set_config(.inst_id (host.name()),
.has_manager (1),
.manager_active_passive (UVM_PASSIVE),
.has_subordinate (0),
.subordinate_active_passive (UVM_PASSIVE),
.has_coverage (0),
.has_checker (0),
.id_width (top_pkg::AxiIdWidth),
.addr_width (top_pkg::AxiAddrWidth),
.data_width (top_pkg::AxiDataWidth),
.user_width (top_pkg::AxiUserWidth),
.region_width ( 4),
.qos_width ( 4)
);
end
endcase
uvm_config_db#(axi4_vip_cfg)::set(this, $sformatf("env.m_mgr_axi_%s*", host.name()),
"m_cfg", axi_mgr_cfg[i]);
end
env.cfg.m_axi_mgr_cfg = axi_mgr_cfg;| axi_sub_name = top_pkg::axi_devices_t'(i); | ||
| axi_sub_cfg[i] = axi4_vip_cfg::type_id::create(.name($sformatf("m_axi_%s_cfg", axi_sub_name.name())), .parent(this)); | ||
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| case (axi_sub_name) |
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This seems way more complicated than it needs to be. I suggest getting rid of the loop and writing out the cases explicitly: it will be shorter and do exactly the same thing.


Tested with top level test cases.
Will close issue #168